This invention relates to a semiconductor device, particularly, a technique effective when adapted to a semiconductor device having a trench-gate structure.
A power transistor has been used for various applications including a power amplifier circuit, power supply circuit, converter and power supply protective circuit. Since it treats high power, it is required to have high breakdown voltage and to permit high current.
In the case of MISFET (Metal Insulator Semiconductor Field Effect Transistor), high current can be attained easily by an expansion of a channel width. In order to avoid an increase in a chip area caused by expansion of a channel width, a mesh-gate structure is, for example, employed.
Gates, are two-dimensionally arranged in the form of a lattice in the mesh-gate structure so that a channel width per unit chip area can be enlarged. A description of an FET having a mesh-gate structure can be found on pages 429 to 430 of xe2x80x9cSemiconductor Handbookxe2x80x9d published by Ohmsha Limited or U.S. Pat. No. 5,940,721.
For such a power FET, a planar structure has conventionally been employed because its fabrication process is simple and an oxide film which will be a gate insulating film can be formed easily. In the above-described U.S. Pat. No. 5,940,721 shown is an FET having a planar structure.
The FET having a planar structure is however accompanied with the drawbacks that when a gate is formed narrowly, the channel length becomes short and a short-channel effect appears because the channel length is determined depending on the gate length; or when a gate is formed narrowly, an allowable current decreases because the gate has additionally a function of wiring. It is therefore impossible to conduct miniaturization freely. With the foregoing in view, adoption of an FET having a trench-gate structure is considered because it can improve the integration degree of cells and in addition, reduce an on resistance.
The trench-gate structure is formed by disposing, via an insulating film, a conductive layer, which will serve as a gate, in a trench extended in the main surface of a semiconductor substrate and in this structure, the deeper portion and the outer surface portion of the main surface serve as a drain region and a source region, respectively and a semiconductor layer between the drain and source regions serves as a channel forming region. Such a structure is described, for example, in U.S. Pat. No. 5,918,114.
The present inventors developed a technique for introducing impurities into a source region or channel forming region of an MISFET having a trench-gate structure after the formation of a trench gate with a view to preventing a deterioration of a gate insulating film or a fluctuation in a threshold voltage owing to the impurities in the source region or channel forming region and have already applied for a patent as U.S. patent application Ser. No. 09/137,508.
With an advance of the miniaturization of a device, there is a tendency to make the source region shallower. When the source region becomes shallower, however, it becomes difficult to place a trench gate at a precise position and the end portion of the trench gate does not overlap with the source region. If a source offset occurs, in other words, the trench gate gets out of the source region, by inaccurate positioning of the trench gate, this source offset impairs the functioning of the FET.
An object of the present invention is to provide a technique capable of overcoming the above-described problem and preventing the occurrence of a source offset.
The above-described and the other objects and novel features of the present invention will be apparent from the description herein and accompanying drawings.
Among the inventions disclosed by the present application, representative ones will next be summarized simply.
Provided is a semiconductor device equipped with an FET of a trench-gate structure having a conductive layer, which will be a gate, disposed in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer or gate electrode is formed equal to or higher than the main surface of the semiconductor substrate.
Also provided is a semiconductor device equipped with an FET of a trench-gate structure having a conductive layer, which will be a gate, disposed in a trench extended in the main surface of a semiconductor substrate, wherein the trench-gate conductive layer (gate electrode) has a substantially flat or convex upper surface and this upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate.
Also provided is a semiconductor device equipped with an FET of a trench-gate structure having a conductive layer, which will be a gate, disposed in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate and the trench gate has, at the terminal portion thereof, a field relaxing portion disposed.
Also provided is a fabrication method of a semiconductor device equipped with an FET of a trench-gate structure having a conductive layer, which will be a gate, disposed in a trench extended in the main surface of a semiconductor substrate, which comprises:
forming a trench, wherein a trench-gate will be formed, in the main surface of the semiconductor substrate;
forming a gate insulating film in the trench,
forming a trench gate in the trench,
forming an insulating film over the main surface of the semiconductor substrate by thermal oxidation so that the film on the trench gate becomes thicker than that on the main surface of the semiconductor substrate by making use of the accelerated oxidation phenomenon,
removing the insulating film by etching and while leaving the thickly formed insulating film on the trench gate, exposing the main surface of the semiconductor substrate, and
selectively removing the semiconductor substrate relative to the insulating film by etching, thereby forming the upper surface of the trench gate covered with the insulating film equal to or higher than the main surface of the semiconductor substrate.
Also provided is a fabrication method of a semiconductor device equipped with an FET of a trench-gate structure having a conductive layer, which will be a gate, disposed in a trench extended in the main surface of a semiconductor substrate, which comprises:
forming a trench, wherein a trench-gate will be formed, on the main surface of the semiconductor substrate;
forming a gate insulating film in the trench,
forming a trench gate in the trench,
forming an insulating film over the main surface of the semiconductor substrate by thermal oxidation so that the film on the trench gate becomes thicker than that on the main surface of the semiconductor substrate by making use of the accelerated oxidation phenomenon,
removing the insulating film by etching and while leaving the thickly formed insulating film on the trench gate, exposing the main surface of the semiconductor substrate,
selectively removing the semiconductor substrate relative to the insulating film by etching, thereby forming the upper surface of the trench gate covered with the insulating film equal to or higher than the main surface of the semiconductor substrate, and
subsequent to the selective etching, introducing impurities from the main surface of the semiconductor substrate, thereby forming a channel forming region and a source region.
Also provided is a fabrication method of a semiconductor device equipped with an FET of a trench-gate structure having a conductive layer, which will be a gate, disposed in a trench extended in the main surface of the semiconductor substrate, which comprises:
forming a trench, wherein a trench-gate will be formed, on the main surface of the semiconductor substrate,
forming a gate insulating film in the trench,
forming a polycrystalline silicon film, which will be a conductive film for the trench gate, all over the main surface of the semiconductor substrate,
removing the polycrystalline silicon film by using etching and multi-stage oxidation in combination, thereby
forming, in the trench, a trench gate having a substantially flat or concave upper surface, forming an insulating film over the main surface of the semiconductor substrate by thermal oxidation so that the film on the trench gate becomes thicker than that on the main surface of the semiconductor substrate by making use of accelerated oxidation phenomenon,
removing the insulating film by etching and while leaving the thickly formed insulating film on the trench gate, exposing the main surface of the semiconductor substrate,
selectively removing the semiconductor substrate relative to the insulating film by etching, thereby forming the upper surface of the trench gate covered with the insulating film equal to or higher than the main surface of the semiconductor substrate, and
subsequent to the selective etching, introducing impurities from the main surface of the semiconductor substrate, thereby forming a channel forming region and a source region.
Described is a fabrication method of a semiconductor device equipped with an FET of a trench-gate structure having a conductive layer, which will be a gate, disposed in a trench extended in the main surface of the semiconductor substrate, which comprises:
disposing a field relaxing portion at the terminal portion of the trench gate,
forming a trench, wherein a trench-gate will be formed, on the main surface of the semiconductor substrate;
forming a gate insulating film in the trench,
forming a trench gate in the trench,
forming an insulating film over the main surface of the semiconductor substrate by thermal oxidation so that the film on the trench gate becomes thicker than that on the main surface of the semiconductor substrate by making use of accelerated oxidation phenomenon,
removing the insulating film by etching and while leaving the thickly formed insulating film on the trench gate, exposing the main surface of the semiconductor substrate,
selectively removing the semiconductor substrate relative to the insulating film by etching, thereby forming the upper surface of the trench gate covered with the insulating film equal to or higher than the main surface of the semiconductor substrate, and
subsequent to the selective etching, introducing impurities from the main surface of the semiconductor substrate, thereby forming a channel forming region and a source region.
Also provided is a fabrication method of a semiconductor device, which comprises:
forming a trench, wherein a trench-gate will be formed, on the main surface of the semiconductor substrate;
forming a gate insulating film in the trench,
forming a trench gate in the trench,
forming an insulating film over the main surface of the semiconductor substrate by thermal oxidation so that the film on the trench gate becomes thicker than that on the main surface of the semiconductor substrate by making use of the accelerated oxidation phenomenon,
forming a mask film over the insulating film on the trench gate,
removing the insulating film by isotropic etching by using the mask film and while leaving the insulating film formed thickly on the trench gate, exposing the main surface of the semiconductor substrate, and
selectively removing the semiconductor substrate relative to the insulating film by etching, thereby forming the upper surface of the trench gate covered with the insulating film equal to or higher than the main surface of the semiconductor substrate.
Also provided is a fabrication method of a semiconductor device, which comprises:
(1) forming a semiconductor layer containing first conductivity type impurities over the main surface of a semiconductor body containing first conductivity type impurities,
(2) forming a field insulating film in a selected region on the main surface of the semiconductor layer,
(3) forming a trench in the semiconductor layer,
(4) forming a gate insulating film over the surface inside of the trench,
(5) embedding a gate layer inside of the trench wherein the gate insulating film has been formed,
(6) etching the main surface of the semiconductor layer so that the main surface of the semiconductor layer becomes lower than the end portion of the gate layer contiguous to the gate insulating film,
(7) introducing second conductivity type impurities in the semiconductor layer, thereby forming, in the semiconductor layer, a first semiconductor region which is positioned shallower than the bottom of the trench and at the same time, is in contact with the gate insulating film, and
(8) introducing first conductivity type impurities in the first semiconductor region, thereby forming, in the first semiconductor region, a second semiconductor region which is positioned shallower than the first semiconductor region and at the same time, is contact with the gate insulating film.
Also provided is a method for fabricating a semiconductor integrated circuit device, which comprises:
etching both an insulating film formed over the main surface of a semiconductor substrate and the semiconductor substrate, thereby forming a connecting hole reaching the inside of the semiconductor substrate,
causing selective retreat of the insulating film relative to the semiconductor substrate, thereby widening the connecting hole so as to expose the main surface of the semiconductor substrate, and
forming a conductive film in the connecting hole.
Also provided is a semiconductor integrated circuit device, wherein a connecting hole is formed in an insulating film formed over the main surface of a semiconductor substrate so as to reach the semiconductor substrate,
the connecting hole has an exposing portion of the main surface of the semiconductor substrate and a portion reaching the semiconductor substrate,
a conductive film is formed in the connecting hole, and
the conductive film is electrically connected with the semiconductor substrate both at the exposing portion of the main surface of the semiconductor substrate and the portion reaching the semiconductor substrate.
By the above-described means, the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate, making it possible to prevent a source offset.